Welcome to Ruoyu Wang's Homepage
Researches & Projects Experience
2T1R Memory Structure Against Single-Event Upset in RRAM Arrays
The single-event upset (SEU) has a significant influence on the reliability of 1-transistor-1-RRAM (1T1R) array due to heavy ion strikes. There was a 1T2R solution to avoid such effect, however, we proposed a novel 2T1R structure which also can alleviate SEU, and has better power efficiency than 1T1R structure. Our simulation result showed that the 2T1R structure achieved 400pJ energy-saving and 1ns delay improvement. This work was published in the IEEE International Conference on ASIC 2019. In this project, I have learned the structure of memory and its working mechanism.
Yu Ma, Dingcheng Jia, Huifan Zhang, Ruoyu Wang and Pingqiang Zhou, "A Compact Memory Structure based on 2T1R against Single-Event Upset in RRAM Arrays," Proceedings of the IEEE International Conference on ASIC (ASION), October 2019.
Optimization of the Power Efficiency on Heterogeneous Multi-core Chips
Energy efficiency is a major concern in heterogeneous multi-core chip, the switching-capacitor converters (SCC) are widely used in multi-core chips. However, SCCs' power loss is a significant partition in the whole loss, therefore, there is an optimization opportunity for efficiency improvement by selecting proper SCC configurations. Moreover, in the real-world multi-core chip, the power requirement varies from time to time, changing SCC configurations dynamically can also diminish the loss. In this project, I have designed the experiment of dynamic on-chip capacitance allocation, then, proposed to lose a model of static allocation by introducing lose caused by Vdroop and implemented it in the scalable experiment code. Then, I have evaluated 4, 8, 16 core chips. Finally, the simulation achieved about 20% efficiency improvement when comparing the static method. We are preparing to publish the work in IEEE Transactions on Computer-Aided Design. In the project, I have learned how to do optimization simulations and practiced academic writing.
Lu Wang, Leilei Wang, Ruoyu Wang and Pingqiang Zhou, "Optimizing the Energy Efficiency of Power Supply in Heterogeneous Multicore Chips with Integrated Switched-Capacitor Converters," Submitted to IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD).
Design Automation Conference (DAC) System Design Contest
The contest was held by the IEEE/ACM Design Automation Conference. It is aimed to design an object-detection inference system on a specific GPU (TX2). Teamed with Zhejiang University, our group designed a yolov3 based inference neural network and deployed it on TX2. I have simplified the inference network architecture, and accelerated the inference from 3fps to 50fps, then enhanced the network design, using feature pyramid network to make the detection of tiny objects more accurate. Finally, we achieved 3rd place out of 52 teams from the world's top universities. The 1st place is the team from the University of Illinois at Urbana-Champaign and 2nd place is the team from Tsinghua University. From the project, I have learned how to design neural networks and how to optimize them, besides, I have learned how to use main-stream neural network frameworks and deploy them on GPU.